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?2006 integrated device technology, inc. november 2006 dsc-3089/06 1 features high-speed access and chip select times ? military: 20/25/35/45/55/70/90/120/150ns (max.) ? industrial: 20/25/35/45ns (max.) ? commercial: 15/20/25/35/45ns (max.) low-power consumption battery backup operation ? 2v data retention voltage (la version only) produced with advanced cmos high-performance technology cmos process virtually eliminates alpha particle soft-error rates input and output directly ttl-compatible static operation: no clocks or refresh required available in ceramic and plastic 24-pin dip, 24-pin thin dip, 24-pin soic and 24-pin soj military product compliant to mil-std-833, class b description the idt6116sa/la is a 16,384-bit high-speed static ram organized as 2k x 8. it is fabricated using idt's high-performance, high-reliability cmos technology. access times as fast as 15ns are available. the circuit also offers a reduced power standby mode. when cs goes high, the circuit will automatically go to, and remain in, a standby power mode, as long as cs remains high. this capability provides significant system level power and cooling savings. the low-power (la) version also offers a battery backup data retention capability where the circuit typically consumes only 1w to 4w operating off a 2v battery. all inputs and outputs of the idt6116sa/la are ttl-compatible. fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. the idt6116sa/la is packaged in 24-pin 600 and 300 mil plastic or ceramic dip, 24-lead gull-wing soic, and 24-lead j-bend soj providing high board-level packing densities. military grade product is manufactured in compliance to the latest version of mil-std-883, class b, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. functional block diagram cs a 0 a 10 i/o 0 i/o 7 oe we 128 x 128 memory array i/o control address decoder input data circuit control circuit gnd 3089 drw 01 v cc , cmos static ram 16k (2k x 8-bit) idt6116sa idt6116la
2 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges pin configurations absolute maximum ratings (1) truth table (1) pin description capacitance (t a = +25c, f = 1.0 mh z ) dip/soic/soj top view 3089 drw 02 5 6 7 8 9 10 11 12 gnd 1 2 3 4 24 23 22 21 20 19 18 17 p24-2 p24-1 d24-2 d24-1 so24-2 so24-4 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 v cc a 9 we a 10 i/o 5 i/o 4 oe 16 15 14 13 a 7 a 6 i/o 7 i/o 6 cs a 8 i/o 2 i/o 3 , note: 1. this parameter is determined by device characterization, but is not production tested. symbol parameter (1) conditions max. unit c in input capacitance v in = 0v 8 pf c i/ o i/o capacitance v out = 0v 8 pf 3089 tbl 03 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v cc +0.5v. symbol rating com'l. mil. unit v te rm (2 ) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t a operating temperature 0 to +70 -55 to +125 o c t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -55 to +125 -65 to +150 o c p t power dissipation 1.0 1.0 w i out dc output current 50 50 ma 3 089 tbl 04 name description a 0 - a 10 address inputs i/o 0 - i/o 7 data input/output cs chip select we write enable oe output enable v cc power gnd ground 3089 tbl 01 note: 1. h = v ih , l = v il , x = don't care. mode cs oe we i/o standby h x x high-z read l l h data out read l h h high-z write l x l data in 3 089 tbl 02
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 3 notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , only address inputs are cycling at f max, f = 0 means address inputs are not changing. dc electrical characteristics (1) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) dc electrical characteristics (v cc = 5.0v 10%) recommended operating temperature and supply voltage recommended dc operating conditions notes: 1. v il (min.) = ?3.0v for pulse width less than 20ns, once per cycle. 2. v in must not exceed v cc +0.5v. grade ambient tem perature gnd vcc military -55 o c to +125 o c0v 5.0v 10% industrial -40 o c to +85 o c0v 5.0v 10% commercial 0 o c to +70 o c0v 5.0v 10% 3089 tbl 05 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 (2) v gnd ground 0 0 0 v v ih input high voltage 2.2 3.5 v cc +0.5 v v il input low voltage -0.5 (1) ____ 0.8 v 3089 tbl 06 symbol parameter test conditions idt6116sa idt6116la unit min. max. min. max. |i li | input leakage current v cc = max., v in = gnd to v cc mil. com'l. ____ ____ 10 5 ____ ____ 5 2 a |i lo | output leakage current v cc = max., cs = v ih , v out = gnd to v cc mil. com'l. ____ ____ 10 5 ____ ____ 5 2 a v ol output low voltage i ol = 8ma, v cc = min. ____ 0.4 ____ 0.4 v v oh output high voltage i oh = -4ma, v cc = min. 2.4 ____ 2.4 ____ v 3089 tbl 0 7 symbol parameter power 6116sa15 6116sa20 6116la20 6116sa25 6116la25 6116sa35 6116la35 unit com'l only com'l & ind mil com'l & ind mil com'l. & ind. mil i cc1 operating power supply current cs < v il , outputs open v cc = max., f = 0 sa 105 105 130 100 90 100 90 ma la 95 95 120 95 85 95 85 i cc2 dynamic operating current cs < v il , outputs open v cc = max., f = f max (2) sa 150 130 150 120 135 100 115 ma la 140 120 140 110 125 95 105 i sb standby power supply current (ttl level) cs > v ih , outputs open v cc = max., f = f max (2) sa 40 40 50 40 45 25 35 ma la 35 35 45 35 40 25 30 i sb1 full standby power supply current (cmos level) cs > v hc , v cc = max., v in < v lc or v in > v hc , f = 0 sa 2 2 10 2 10 2 10 ma la 0.1 0.1 0.9 0.1 0.9 0.1 0.9 3089 tbl 08
4 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges notes: 1. t a = + 25c 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization, but is not production tested. dc electrical characteristics (1) (continued) (v cc = 5.0v 10%, v lc = 0.2v, v hc = v cc - 0.2v) notes: 1. all values are maximum guaranteed values. 2. f max = 1/t rc , only address inputs are toggling at f max , f = 0 means address inputs are not changing. data retention characteristics over all temperature ranges (la version only) (v lc = 0.2v, v hc = v cc ? 0.2v) symbol parameter power 6116sa45 6116la45 6116sa55 6116la55 6116sa70 6116la70 6116sa90 6116la90 6116sa120 6116la120 6116sa150 6116la150 unit com'l & ind mil mil only mil only mil only mil only mil only i cc1 operating power supply current, cs < v il , outputs open v cc = max., f = 0 sa 100 90 90 90 90 90 90 ma la 95 85 85 85 85 85 85 i cc2 dynamic operating current, cs < v il , outputs open v cc = max., f = f max (2) sa 100 100 100 100 100 100 90 ma la 90 95 90 90 85 85 85 i sb standby power supply current (ttl level) cs > v ih , outputs open v cc = max., f = f max (2) sa 25 25 25 25 25 25 25 ma la 20 20 20 20 25 15 15 i sb1 full standby power supply current (cmos level), cs > v hc , v cc = max., v in < v lc or v in > v hc , f = 0 sa2101010101010 ma la 0.1 0.9 0.9 0.9 0.9 0.9 0.9 3089 tbl 09 typ. (1 ) v cc @ max. v cc @ symbol parameter test condition min. 2.0v 3.0v 2.0v 3.0v unit v dr v cc fo r data re te ntio n ____ 2.0 ____ ____ ____ ____ v i ccdr data retention current mil. com'l. ____ ____ 0.5 0.5 1.5 1.5 200 20 300 30 a t cd r (3) chip deselect to data retention time cs > v hc v in > v hc or < v lc ____ 0 ____ ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ____ ____ ns i i li i input leakage current ____ ____ ____ 22 a 3089 tbl 10
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 5 low v cc data retention waveform ac test conditions data retention mode v cc cs t cdr 4.5v v dr 2v v dr 4.5v t r v ih v ih 3089 drw 03 , figure 2. ac test load (for t olz , t clz , t ohz , t whz , t chz & t ow ) figure 1. ac test load *including scope and jig. 3089 drw 04 30pf* 255 ? 5v data out 480 ? , 5pf* 255 ? 5v 480 ? data out 3089 drw 05 , input pulse levels input rise/fall times input timing reference levels output reference levels ac test load gnd to 3.0v 5ns 1.5v 1.5v see figures 1 and 2 3089 tbl 11
6 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ac electrical characteristics (v cc = 5v 10%, all temperature ranges) (continued) notes: 1. 0c to +70c temperature range only. 2. ?55c to +125c temperature range only. 3. this parameter guaranteed with the ac load (figure 2) by device characterization, but is not production tested. ac electrical characteristics (v cc = 5v 10%, all temperature ranges) symbol parameter 6116sa15 (1) 6116sa20 6116la20 6116sa25 6116la25 6116sa35 6116la35 unit min. max. min. max. min. max. min. max. read cycle t rc read cycle time 15 ____ 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 15 ____ 19 ____ 25 ____ 35 ns t acs chip select access time ____ 15 ____ 20 ____ 25 ____ 35 ns t clz (3 ) chip select to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ ns t oe output enable to output valid ____ 10 ____ 10 ____ 13 ____ 20 ns t ol z (3) output enable to output in low-z 0 ____ 0 ____ 5 ____ 5 ____ ns t chz (3 ) chip de se lect to output in high-z ____ 10 ____ 11 ____ 12 ____ 15 ns t ohz (3) output dis able to output in high-z ____ 8 ____ 8 ____ 10 ____ 13 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ ns t pu (3 ) chip s elect to power up time 0 ____ 0 ____ 0 ____ 0 ____ ns t pd (3 ) chip desele ct to power down time ____ 15 ____ 20 ____ 25 ____ 35 ns 3089 tbl 12 symbol parameter 6116sa45 6116la45 6116sa55 (2 ) 6116la55 (2 ) 6116sa70 (2 ) 6116la70 (2) 6116sa90 (2 ) 6116la90 (2 ) 6116sa120 (2 ) 6116la120 (2 ) 6116sa150 (2 ) 6116la150 (2 ) unit min. max. min. max. min. max. min. max. min. max. min. max. read cycle t rc read cycle time 45 ____ 55 ____ 70 ____ 90 ____ 120 ____ 150 ____ ns t aa address access time ____ 45 ____ 55 ____ 70 ____ 90 ____ 120 ____ 150 ns t acs chip select access time ____ 45 ____ 50 ____ 65 ____ 90 ____ 120 ____ 150 ns t clz (3 ) chip select to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ ns t oe output enable to output valid ____ 25 ____ 40 ____ 50 ____ 60 ____ 80 ____ 100 ns t ol z (3) output enable to output in low-z 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ ns t chz (3 ) chip de se lect to output in high-z ____ 20 ____ 30 ____ 35 ____ 40 ____ 40 ____ 40 ns t ohz (3) output dis able to output in high-z ____ 15 ____ 30 ____ 35 ____ 40 ____ 40 ____ 40 ns t oh output hold from address change 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ 5 ____ ns 3089 tbl 13
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 7 timing waveform of read cycle no. 2 (1,2,4) timing waveform of read cycle no. 1 (1,3) timing waveform of read cycle no. 3 (1,3,4) notes: 1. we is high for read cycle. 2. device is continously selected, cs is low. 3. address valid prior to or coincident with cs transition low. 4. oe is low. 5. transition is measured 500mv from steady state. address oe cs t rc t aa t oe t acs data out t oh t olz (5) t clz (5) t ohz (5) t chz (5) 3089 drw 06 data valid t pd i cc i sb t pu v cc supply currents , address t rc t aa t oh t oh data out 3089 drw 07 previous data valid data valid , cs t acs data out t clz (5) t chz (5) data valid 3089 drw 08 ,
8 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ac electrical characteristics (v cc = 5v 10%, all temperature ranges) notes: 1. 0c to +70c temperature range only. 2. ?55c to +125c temperature range only. 3. this parameter guaranteed with ac load (figure 2) by device characterization, but is not production tested. 4. the specification for t dh must be met by the device supplying write data to the ram under all operation conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . ac electrical characteristics (v cc = 5v 10%, all temperature ranges) (continued) 6116sa15 (1 ) 6116sa20 6116la20 6116sa25 6116la25 6116sa35 6116la35 symbol parameter min. max. min. max. min. max. min. max. unit write cycle t wc write cycle time 15 ____ 20 ____ 25 ____ 35 ____ ns t cw chip select to end-of-write 13 ____ 15 ____ 17 ____ 25 ____ ns t aw address valid to end-of-write 14 ____ 15 ____ 17 ____ 25 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ 0 ____ ns t wp write pulse width 12 ____ 12 ____ 15 ____ 20 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ 0 ____ ns t whz (3 ) write to output in high-z ____ 7 ____ 8 ____ 16 ____ 20 ns t dw data to write time overlap 12 ____ 12 ____ 13 ____ 15 ____ ns t dh (4 ) data hold from write time 0 ____ 0 ____ 0 ____ 0 ____ ns t ow (3,4) output active fro m end-of-write 0 ____ 0 ____ 0 ____ 0 ____ ns 3089 tbl 14 6116sa45 6116la45 6116sa55 (2 ) 6116la55 (2 ) 6116sa70 (2 ) 6116la70 (2 ) 6116sa90 (2 ) 6116la90 (2 ) 6116sa120 (2) 6116la120 (2) 6116sa150 (2) 6116la150 (2) symbol parameter min. max. min. max. min. max. min. max. min. max. min. max. unit write cycle t wc write cycle time 45 ____ 55 ____ 70 ____ 90 ____ 120 ____ 150 ____ ns t cw chip select to end-of-write 30 ____ 40 ____ 40 ____ 55 ____ 70 ____ 90 ____ ns t aw address valid to end-of-write 30 ____ 45 ____ 65 ____ 80 ____ 105 ____ 120 ____ ns t as address set-up time 0 ____ 5 ____ 15 ____ 15 ____ 20 ____ 20 ____ ns t wp write pulse width 25 ____ 40 ____ 40 ____ 55 ____ 70 ____ 90 ____ ns t wr write recovery time 0 ____ 5 ____ 5 ____ 5 ____ 5 ____ 10 ____ ns t whz (3 ) write to output in high-z ____ 25 ____ 30 ____ 35 ____ 40 ____ 40 ____ 40 ns t dw data to write time overlap 20 ____ 25 ____ 30 ____ 30 ____ 35 ____ 40 ____ ns t dh (4 ) data hold from write time 0 ____ 5 ____ 5 ____ 5 ____ 5 ____ 10 ____ ns t ow (3,4) output active fro m end-of-write 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns 3089 tbl 15
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 9 timing waveform of write cycle no. 1 ( we controlled timing) (1,2,5,7) timing waveform of write cycle no. 2 ( cs controlled timing) (1,2,3,5,7) notes: 1. we or cs must be high during all address transitions. 2. a write occurs during the overlap of a low cs and a low we . 3. t wr is measured from the earlier of cs or we going high to the end of the write cycle. 4. during this period, the i/o pins are in the output state and the input signals must not be applied. 5. if the cs low transition occurs simultaneously with or after the we low transition, the outputs remain in the high-impedance state. 6. transition is measured 500mv from steady state. 7. oe is continuously high. if oe is low during a we controlled write cycle, the write pulse width must be the larger of t wp or (t whz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe is high during a we controlled write cycle, this requirement does not apply and the write pulse is the specified t wp . for a cs controlled write cycle, oe may be low with no degradation to t cw . address data out cs we data in t wc t aw 3089 drw 09 t as t whz (6) (4) t dw t dh (4) t ow t wr t chz (6) t wp (7) (6) previous data valid data valid data valid (3) , cs we data in t wc t aw t cw t wr (3) t dw t dh t as 3089 drw 10 data valid address ,
10 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges ordering information ? military blank i tp p so y 15* 20 25 35 45 sa la commercial (0c to +70c) industrial (-40c to +85c) 300 mil plastic dip (p24-1) 600 mil plastic dip (p24-2) 300 mil small outline ic, gull-wing bend (so24-2) 300 mil soj, j-bend (so24-4) standard power low power idt 6116 device type xx power xxx speed x package x process/ temperature range 3089 drw 12 speed in nanoseconds , *available in commercial temperature range and standard power only. x g restricted hazardous substance device ordering information ? commercial & industrial b td d 20* 25* 35* 45 55 70 90 120 150** sa la military (-55c to +125c) compliant to mil-std-883, class b 300 mil cerdip (d24-1) 600 mil cerdip (d24-2) standard power low power idt 6116 device type xx power xxx speed x package x process/ temperature range 3089 drw 11 speed in nanoseconds , *available in 300 mil packaging only. **available in 600 mil packaging only.
6.42 idt6116sa/la cmos static ram 2k (16k x 8-bit) military, commercial, and in dustrial temperature ranges 11 datasheet document history 1/7/00 updated to new format pg. 1, 3, 4, 10 added industrial temperature range offerings pg. 9, 10 separated ordering information into military, commercial, and industrial temperature range offerings pg. 11 added datasheet document history 08/09/00 not recommended for new designs 02/01/01 removed "not recommended for new designs" 12/30/03 pg. 3,10 corrected industrial temp from -45c to -40c. 03/31/05 pg. 10 added "restricted hazardous substance device" to ordering information. 11/15/06 pg. 3 c hanged power limits for commercial and industrial on speed grades 25ns and 35ns. pg.4 changed powe limits for commercial and industrial on speed grade 45ns. refer to pcn sr-0602-02. the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or ipchelp@idt.com san jose, ca 95138 408-284-8200 800-345-7015 fax: 408-284-2775 www.idt.com
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